Using the ChipScope Pro for Testing HDL Designs on FPGAs
Introduction:
Simulation based method is widely used for debugging the FPGA design on computers. Time required for simulating complex design for all possible test cases becomes prohibitively large and simulation approach fails. For rapid testing, such designs can be loaded on to the target FPGAs and tested by applying test inputs and directly observing their outputs. As the complexity of the design under test increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope Pro tools integrate key logic analyzer and other test and measurement hardware components with the target design inside the FPGA. Computer based software tool communicate with these hardware components and provide a designer robust logic analyzer solution.
In this tutorial we will use simple UP counter design and test it using ChipScope.
You can download the PDF file of this tutorial from here.
